Design Verification Engineer

Location: Munich, Bavaria, Germany

Type: Full Time

Min. Experience: Mid Level

Verilab is an international professional services team of verification experts. Founded in 2000, we specialize in solving the toughest functional verification problems for ASIC, FPGA and independent IP development. Our work ranges from rescuing projects struggling with verification, through sophisticated verification IP development, to complete methodology engineering. We innovate, implement, manage and coach.

Job Description:
We invite you to join a highly motivated team of verification consultants to push the boundaries of the verification space as we know it today and provide our end-clients with the very best in verification excellence. Working as part of a team, you would be responsible for the development of state-of-the art verification environments under the guidance and mentoring of our technical leads. Flexibility to travel is required.


  • BSc/MSc in EE with at least 4 years of project proven verification experience.
  • Constrained-Random Verification: experience in using SystemVerilog/UVM to implement all aspects of a block-level verification environment including: sequence-based stimulus; functional coverage; transaction-level checkers (e.g. scoreboards) and assertion-based protocol checks. Specman/e expertise to a similar level, combined with an understanding of SV/UVM, would also be considered. Some exposure to system-level is an advantage.

What we offer you:
Exposure to a wide cross-section of clients and target domains, combined with the ability to work alongside some of the smartest people in the industry today, Verilab is a small company where your skills will be tested and also nurtured, where your contribution will make a difference


  • Full-time permanent employee with competitive salary
  • 30 Days Paid Holidays and Statutory days

All candidates must be eligible to work in the EU.

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